Information, such as information representing audio, video and multimedia content, can be transferred within a computer system. Consider, for example, FIG. 1, which illustrates a known architecture for connecting an external Input/Output (IO) device 10 to a computer system 100. The computer system 100 includes a processor 110 coupled to a main memory 200 through a memory controller 300. The external IO device 10 communicates with an IO unit 400, which is also coupled to the memory controller 300.
The external IO device 10 can, for example, transfer “asynchronous” information with the IO unit 400, which in turn transfers information with the memory controller 300. When a transfer of information is asynchronous, delays can occur that interfere with the timely completion of the transfer. Typically, other, more important, activities can delay an information transfer without adversely impacting system performance. In some types of information streams, however, even a minor delay or gap will noticeably degrade the quality of the information, such as by causing a momentary freeze in a video transmission or by introducing a stuttering effect in an audio transmission.
When a transfer of information is “isochronous,” a sending and receiving device are partly synchronized, generally without using the same clock signal, and the sending device transfers information to the receiving device at regular intervals. Such transfers can be used, for example, when information needs to arrive at the receiving device at the same rate it is sent from the sending device, but without precise synchronization of each individual data item. The IEEE 1394 standard (1995), entitled “High Performance Serial Bus” and available from the Institute of Electrical and Electronic Engineers, is one example of an interface that supports the isochronous transfer of information.
In addition to the isochronous transfer of information between the external IO device 10 and the computer system 100, the transfer of information within the computer system 100 may also be isochronous. U.S. patent application Ser. No. 09/110,344, entitled “Architecture for the Isochronous Transfer of Information Within a Computer System,” to John I. Garney and Brent S. Baxter, filed on Jul. 6, 1998 and assigned to Intel Corporation, discloses an architecture that provides for the isochronous transfer of information within a computer system.
In this case, the IO unit 400 may perform both isochronous and asynchronous information transfers, or “transactions,” with the memory controller 300. In addition, the IO unit 400 may have several different transactions to be sent to (or received from) the memory controller 300 at substantially the same time. Similarly, the memory controller 300 may have several different transactions to be sent to (or received from) the IO unit 400.
The connection 500, or “link,” between the IO unit 400 and the memory controller 300, however, is typically a “half duplex” link. A half duplex link between two devices is one that lets information be transferred in both directions, that is from the first to the second device and from the second to the first device, but not in both directions at the same time.
Because both the IO unit 400 and the memory controller 300 may each have information that is ready to be transferred over the half duplex link 500, or transactions that are “ready to be serviced,” particular transactions can be selected to be transferred across the link 500, or “scheduled.” Such scheduling poses a number of problems. For example, if an asynchronous transaction is scheduled when an isochronous transaction is ready to be serviced, the benefits of using an isochronous stream of information, such as making sure that information flows continuously and at a steady rate, may be reduced or lost altogether.
To solve this problem, one or more large data buffers, such as one or more First-In, First-Out (FIFO) data buffers, can be provided to store isochronous information when the half duplex link 500 cannot be accessed. In this case, information being transferred, for example, between the IO device 10 and the main memory 200 can be stored to, or retrieved from, various buffers when the half duplex link 500 is not available. This buffering can accommodate delays thereby reducing the gaps in an isochronous stream within the computer system 100. Such buffering, however, may increase the cost, lower the performance and make the computer system 100 more difficult to build and test. Moreover, information within the computer system 100 may still not be transferred in a reliable and timely fashion if the delays are too long.